1. Technical Field
The present disclosure relates to the forming of Shallow Trench Insulation (STI), to separate electronic components formed on a silicon-on-insulator or SOI type wafer. The present disclosure more specifically aims at the forming of trenches in structures where the thin single-crystal silicon structure formed on an insulator has a very small thickness, for example, approximately in the range of 5 to 25 nm, and the insulating layer on which this thin single-crystal silicon layer lies also has a small thickness, approximately in the range of 10 to 50 nm.
2. Discussion of the Art
FIG. 1A shows an SOI wafer comprising a single crystal silicon support 3 coated with an insulating silicon oxide layer 5 (SiO2) coated with a thin single-crystal silicon layer 7. This wafer is coated with a hard mask comprising a thin SiO2 layer 11 coated with a silicon nitride layer (Si3N4) 13. After a masking step, a trench 15 has been formed by anisotropic etch methods, generally comprising plasma etchings adapted to the various materials to be etched. Trench 15 crosses masking layers 11 and 13, single-crystal silicon layer 7, and insulator layer 5, and penetrates into silicon support 3. As an example, the case where the trench has a width approximately in the range of 40 to 100 nm and a depth approximately in the range of 100 to 300 nm, where oxide layer 5 has a thickness approximately in the range of 10 to 50 nm, for example, 30 nm, and where thin single-crystal silicon layer 7 has a thickness approximately in the range of 5 to 25 nm, for example, 10 nm, is considered herein. After the trench has been formed, a thermal oxidation step is carried out, whereby an SiO2 cladding 17 forms on the exposed surface of single-crystal silicon layer 7 and an SiO2 cladding 19 forms on the exposed surface of silicon support 3.
As illustrated in FIG. 1B, silicon oxide is then deposited by low-temperature chemical deposition so that this oxide 20 fills trench 15. Silicon oxide of a given thickness is thus inevitably present above the wafer.
After this, as illustrated in FIG. 1C, all that has been formed or deposited on the wafer above thin silicon layer 7 is removed. This removal may for example first be performed by chem.-mech. polishing of the upper portion of silicon oxide 20 and of silicon nitride 13. This etching stops when silicon oxide layer 11 has been reached. After this, silicon oxide 11 is selectively etched to obtain a topography of the type illustrated in FIG. 1C where the upper surface of silicon oxide 20 filling trench 1 is slightly below the upper level of single-crystal silicon layer 7, while there only remains a lower portion of thermal SiO2 cladding 17. Further, currently, the exposed surface of filling silicon oxide 20 is lower at the interface with silicon 7 than in the middle of the trench.
It should be noted that the etching operations must be performed with special care, given the very small thickness (on the order of 10 nm) of layer 7, which means that the etching of oxide 20 must be performed with a precision to within from 1 to 2 nm to avoid for the oxide filling the trench to lower below the silicon level.
Despite all these precautions, as illustrated in FIG. 1D, the upper level of oxide filling 20 tends to lower in subsequent wafer processing. Indeed, during such subsequent processing, there inevitably are oxide layer etching phases and the etching process also acts on oxide 20 and especially on its edges where craters 22 (actually, a ring) tend to form. This lowering of oxide 20 may cause a deterioration of the components subsequently formed in thin silicon layer 7 if this causes a decrease in the thickness of insulating layer 5.
There thus is a need to improve the filling of shallow trenches with insulator, essentially in the context of SOI-type technologies where a very thin silicon layer (having a thickness approximately in the range of 5 to 25 nm) is formed on a thin insulating layer (having a thickness approximately in the range of 10 to 50 nm).